1. Field of the Invention
The present invention relates to a method and apparatus for modeling source-drain current of a thin film transistor (TFT). More particularly, the present invention relates to a method and apparatus for modeling source-drain current of a TFT, which can be applied to oxide TFTs and organic TFTs, as well as amorphous silicon TFTs.
This work was supported by the IT R&D program of MIC/IITA [2006-S-079-02, Smart window with transparent electronic devices].
2. Discussion of Related Art
Conventional transistor prediction modeling scheme for silicon MOSFETs (eg. AIM-SPICE, Silvaco-UTMOST, etc.) has been applied to amorphous or polycrystalline silicon thin film transistors (TFTs) used as switching or driving transistors for a display, such as an Active Matrix Liquid Crystal Display (AM LCD) or an Active Matrix-Organic Light-Emitting Diode (AM-OLED). However, since such conventional prediction model for silicon TFTs is not well applied to oxide (ZnO-based) semiconductor TFTs, which is recently expected to be used to transparent panels and flexible panels, it is difficult to perform element analysis and circuit design for the oxide TFTs.
This is because defects on numerous crystal boundaries in an oxide semiconductor TFT having nano-crystallinity trap most electrons induced by a gate bias and there is a characteristic that electron mobility itself is represented as a function of the gate bias. It is also difficult to directly apply a model for amorphous silicon TFTs to InGa—ZnO (IGZO) TFTs due to a high density of defects. Thus, there is a need for a prediction modeling method capable of being applied to organic TFTs and oxide TFTs, as well as amorphous TFTs.